(1) Field of the Invention
The invention relates to a method of copper metallization in the fabrication of integrated circuits, and more particularly, to a method of reducing the formation of copper hillocks in copper metallization in the manufacture of integrated circuits.
(2) Description of the Prior Art
In a common application for integrated circuit fabrication, a contact/via opening is etched through an insulating layer to an underlying conductive area to which electrical contact is to be made. A conducting layer material is deposited within the contact/via opening. Because of its lower bulk resistivity, Copper (Cu) metallization is the future technology for feature sizes of 0.18 microns and below. Often, a damascene or dual damascene process is used to provide Cu metallization. The copper is deposited within the damascene opening and polished back. Then, a capping layer, such as silicon nitride or silicon carbide, is deposited over the copper plugs to prevent copper from diffusing into overlying layers.
During the deposition of the capping layer, the thermal budget will induce compressive-thermal stress on the copper, causing a vertical strain on the copper surface. FIG. 1A illustrates a copper damascene line 20 within an insulating layer 18 on a substrate 10. Copper oxide 22 has formed naturally on the surface of the copper after planarization. FIG. 1B shows the compressive-thermal stress 30 acting along grain boundaries within the copper during deposition of the capping layer 40. FIG. 1C shows copper hillocks 32 formed by the vertical thermal strain on the copper surface. Copper hillocks reduce copper reliability, cause via induced metal island corrosion (VIMIC), and confuse defect inspection tools so that other defects cannot be detected accurately. Reduction of copper hillocks in the copper damascene process becomes more and more important for yield and reliability improvement. It is desired to reduce copper hillock generation in the copper metallization process.
Co-pending U.S. patent application Ser. No. 09/998,787 (TS00-863), filed on Oct. 31, 2001, to the same assignee as the present invention discloses a method of reducing copper hillocks by 1) pre-coating an oxide layer on the deposition chamber walls, 2) using NH3 plasma rather than NH3 gas in the deposition chamber, and 3) keeping the time between copper CMP and capping layer deposition to less than one day (24 hours). U.S. Pat. No. 6,355,571 to Huang et al discloses the use of NH3 or H2 to reduce CuO to copper and an in-situ deposition of a capping layer. U.S. Pat. No. 6,506,677 Avanzino et al and U.S. Pat. No. 6,429,128 to Besser et al teach NH3 and N2 plasma to reduce CuO to Cu and an in-situ deposition of a capping layer. Besser et al alternatively teaches depositing the capping layer at reduced RF power and increased spacing to reduce compressive stress. U.S. Pat. No. 5,654,232 to Gardner teaches a copper damascene process. U.S. Pat. No. 6,482,755 to Ngo et al shows treatment in NH3, NH2, or H2 plasma at a reduced temperature to reduce CuO to Cu, then in-situ deposition of HDP silicon nitride. U.S. Pat. No. 6,515,373 to Barth describes annealing before and/or after CMP to reduce hillocks. U.S. Pat. No. 6,500,754 to Erb et al discloses annealing prior to CMP wherein the annealing stimulates grain growth to prevent hillock formation.